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MAX14895E enhanced vga port protector ????????????????????????????????????????????????????????????????? maxim integrated products 1 general description the MAX14895E integrates level-translating buffers and features red, grn, and blu (rgb) port protection for vga signals. the device has horizontal sync (synch_) and vertical sync (syncv_) translating buffers that convert low-level cmos inputs from a graphics controller to meet full 5v, ttl-compatible outputs. each output can drive q10ma and meets the vesa sm specification. in addition, the device translates the direct digital control (ddc) signals to a lower level that is safe for the graphics controller. the device features both en and en inputs, accepting active-high or active-low enable inputs. the device also switches and current limits the 5v supply to a vga con - nector or monitor. the red, grn, and blu terminals protect graphics con - troller outputs against electrostatic discharge (esd) events. all eight outputs and en have high-level esd protection. the MAX14895E is specified over the extended -40 n c to +85n c temperature range and is available in a 16-pin, 3mm x 3mm tqfn package with exposed pad. applications benefits and features s saves power in portable applications ? low quiescent supply current: 430a (typ) s eliminates need for costly external components ? high-esd protection on sda1, scl1, synch1, syncv1, red, grn, blu, en , v s ? 15kv human body model (hbm) ? 8kv iec 61000-4-2 contact discharge s innovative design enables a high level of integration for performance ? output current-limit switch with power-off protection ? low capacitance on rgb ports (2.2pf typ) ? 10ma drive on synch1, syncv1 s fully integrated solutions saves space in portable applications ? ddc outputs have internal pullups ? 3mm x 3mm, 16-pin tqfn package typical operating circuit 19-5819; rev 0; 3/11 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX14895E.related. notebook computers desktops servers graphics cards vesa is a service mark of the video electronics standards association corporation. e v a l u a t i o n k i t a v a i l a b l e MAX14895E +5v v cc v s en gnd 1f 1f en synch0, syncv0 vga outputs vga port 2 sda0, scl0 red grn blu synch1, syncv1 sda1, scl1 2 2 2 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 MAX14895E enhanced vga port protector (voltages referenced to gnd.) v cc , v s , en, sda0, scl0 ...................................... -0.3v to +6v sda1, scl1 ................................................ -0.3v to (v s + 0.3v) en , red, grn, blu, synch0, synch1, syncv0, syncv1 ................ -0.3v to (v cc + 0.3v) continuous current through sda_, scl_ ....................... q 30ma continuous short-circuit current synch1, syncv1 ..... q 20ma continuous power dissipation (t a = +70 n c) tqfn (derate 20.8mw/ n c above +70 n c) .................. 1667mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) .......... 48 n c/w junction-to-case thermal resistance ( b jc ) ................. 7 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v cc = +4.75v to +5.25v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +5v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max units power supply power-supply range v cc 4.75 5.25 v quiescent supply current i q en = v cc , en = gnd, synch0 = syncv0 = gnd, sda0 = scl0 = unconnected 430 800 f a shutdown supply current i shdn en = gnd, en = v cc , synch0 = syncv0 = gnd, sda0 = scl0 = unconnected 8 f a undervoltage lockout threshold v uvlo v cc rising 4.3 v undervoltage lockout hysteresis 0.1 v internal logic supply voltage v l v cc = +4.75v to +5.25v, sda1/scl1 = unconnected, measure sda0/scl0 1.6 2.9 v v cc = +4.75v to +5.25v, sda0/scl0 = 200k i to gnd, measure sda0/scl0, sda1/scl1 = unconnected 1.6 2.8 red, grn, blu red, grn, blu capacitance c out f = 1mhz, v red, grn, blu = 1v p-p 2.2 pf red, grn, blu leakage current -1 +1 f a synch0, syncv0, en, en input logic-high v ih 2.0 v input logic-low v il 0.8 v * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede values quoted elsewhere in this data sheet.
????????????????????????????????????????????????????????????????? maxim integrated products 3 MAX14895E enhanced vga port protector note 2: all devices are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and not production tested. note 3: guaranteed by design. electrical characteristics* (continued) (v cc = +4.75v to +5.25v, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at v cc = +5v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max units synch0, syncv0 leakage current synch0/syncv0 = gnd or v cc -1 +1 f a en, en input resistance en = v cc , en = gnd 200 800 k i synch1, syncv1 output logic-high v oh v cc = +4.75v, source 10ma 2.4 v output logic-low v ol v cc = +4.75v, sink 10ma 0.5 v rising time t r r l = 2.2k i , c l = 10pf, 10% to 90% of v cc (note 3) 4 ns falling time t f r l = 2.2k i , c l = 10pf, 90% to 10% of v cc (note 3) 4 ns propagation delay t pd r l = 2.2k i , c l = 10pf, en = v cc , en = gnd ( figure 1 ) 16 ns enable time t en r l = 2.2k i , c l = 10pf, v synch1, v syncv1 = +4.75v ( figure 1 ) 17 f s sda?, scl? (ddc) on-resistance r on v sda0 = v scl0 = 0.5v, i load = 10ma 55 i sda0, scl0 off-leakage current en = gnd, en = v cc , sda0 = scl0 = v cc , sda1 = scl1 = gnd -1 +1 f a sda1, scl1 reverse-leakage current v cc = 0v, v s = +5.25v, v sda1 = v scl1 = +5.25v -10 +10 f a sda1, scl1 pullup resistor r pullup v cc = +4.75v, sda0 = scl0 = unconnected, en = v cc , en = gnd, i load = 100 f a 1.25 2.5 4.0 k i v s output forward voltage drop i load = 60ma, v cc = 5v 0.25 v reverse-leakage current v cc = 0v, v s = 5.25v 10 f a current limit i lim 200 600 ma discharge resistor r vs i load = 1ma 300 500 i thermal shutdown thermal shutdown threshold +150 n c thermal shutdown hysteresis 10 n c esd protection sda1, scl1, synch1, syncv1, red, grn, blu, en , v s hbm 15 kv iec 61000-4-2 contact 8 kv * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede values quoted elsewhere in this data sheet.
????????????????????????????????????????????????????????????????? maxim integrated products 4 MAX14895E enhanced vga port protector figure 1. timing diagram 50% 50% 50% 50% t phl t pd = max(t plh , t phl ) 2.4v 0v output high output low 2.4v 2.4v 0v 0v output high output low v synch0 /v syncv0 v en v en v synch1 /v syncv1 v synch1 /v syncv1 50% 50% 50% t plh t en
????????????????????????????????????????????????????????????????? maxim integrated products 5 MAX14895E enhanced vga port protector typical operating characteristics (v cc = +5v, t a = +25 n c, unless otherwise noted.) on-resistance vs. sda0 voltage MAX14895E toc01 v sda0 (v) r on () 2.5 2.0 0.5 1.0 1.5 10 20 30 40 50 60 70 80 0 0 3.0 sda0, scl0 are interchangeabl e t a = -40c t a = +25c t a = +85c hv buffer output-voltage high vs. temperature MAX14895E toc02 temperature (c) output voltage (v) 60 35 10 -15 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 4.0 -40 85 i out = 8ma hv buffer output-voltage low vs. temperature MAX14895E toc03 temperature (c) output voltage (v) 60 35 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 85 i out = 8ma
????????????????????????????????????????????????????????????????? maxim integrated products 6 MAX14895E enhanced vga port protector pin configuration pin description pin name function 1 red high-esd protection diodes for rgb signals 2 grn high-esd protection diodes for rgb signals 3 blu high-esd protection diodes for rgb signals 4 gnd ground 5 v s supply voltage output with current-limit switch. v s provides a current-limited voltage from v cc when the device is enabled. bypass v s to gnd with a 1 f f or larger ceramic capacitor as close as possible to the device. 6 en active-low enable input. drive en high and en low to disable the device. en is weakly pulled up internally. 7 sda0 ddc data input from graphics controller 8 sda1 ddc data output to vga monitor. internally pulled up to v cc . 9 scl0 ddc clock input from graphics controller 10 scl1 ddc clock output to vga monitor. internally pulled up to v cc . 11 synch0 horizontal sync input 12 synch1 horizontal sync output 13 syncv0 vertical sync input 14 syncv1 vertical sync output 15 v cc supply voltage input. apply a voltage between +4.75v and +5.25v to v cc to power the device. bypass v cc to gnd with a 1 f f or larger ceramic capacitor as close as possible to the device. 16 en active-high enable input. drive en low and en high to disable the device. en is weakly pulled down internally. ep exposed pad. connect ep to gnd. for enhanced thermal dissipation, connect ep to a large ground plane. do not use ep as the only ground connection. 15 16 14 13 5 6 7 blu gnd 8 red scl1 scl0 synch1 1 3 syncv1 4 12 10 9 v cc en *ep *connect ep to gnd. sda1 sda0 en v s grn synch0 2 11 syncv0 tqfn (3mm x 3mm) top view + MAX14895E
????????????????????????????????????????????????????????????????? maxim integrated products 7 MAX14895E enhanced vga port protector functional diagram/truth table MAX14895E current-limit switch v cc en en sda0 scl0 sda1 v s scl1 synch0 synch1 logic thermal shutdown high esd r pullup r pullup r vs sda/scl pullup resistor switches v s pullup-to-gnd switches i 2 c level shifter high esd high esd high esd high esd high esd high esd gnd syncv0 red high esd grn high esd blu syncv1 device logic en en enable 0 0 disable 1 0 enable enable 0 1 disable output 0v device logic/ event synch_/syncv_ buffer enable no overcurrent i 2 c level shifter on current -limit switch on sda/scl pullup resistor switches on v s pull-to-gnd switch off on enable overcurrent on current limit on off on enable overcurrent thermal shutdown off off off on off off off on v cc = 0v off off off off off output 0v 1 1
????????????????????????????????????????????????????????????????? maxim integrated products 8 MAX14895E enhanced vga port protector detailed description the MAX14895E integrates level-translating buffers and features red, grn, and blu port protection for vga sig - nals. horizontal and vertical synchronization (synch0, syncv0) inputs feature level-shifting buffers to support low-voltage cmos or standard ttl-compatible graphics controllers. each output can drive q 10ma and meets vesa specifications. the device also features i 2 c level shifting using two nmos devices. the device generates its own internal bias supply to clamp scl0 and sda0 to a safe level, removing the need for another external supply. the device also provides a current-limited v cc output with power-off protection. this output can be used to switch power to a vga connector or the vga interface of a monitor. horizontal/vertical sync level shifter synch0 and syncv0 are buffered to provide level shift - ing and drive capability to meet the vesa specification. the level-shifted outputs (synch1, syncv1) are pulled low when en is low and en is high, or when the device is in thermal shutdown (see the functional diagram/ truth table ). logic-level outputs (v ol , v oh ) are 5v ttl- compatible. these two buffers are identical and each can drive either the horizontal or the vertical synch signal. display data channel switches the device incorporates two nmos switches for i 2 c level shifting. the sda0 and scl0 terminals are voltage clamped to a diode drop less than the internal v l volt - age. voltage clamping provides protection and compat - ibility with the sda0 and scl0 signals and low-voltage asics. when power is off (v cc = 0v), sda1 and scl1 are protected against reverse-leakage current up to v s = +5.25v. the sda_ and scl_ switches are identical, and each switch can be used to route sda_ or scl_ signals. rgb ports the device includes three terminals for red, grn, and blu signals. these terminals provide high-level esd pro - tection to the rgb lines while keeping the capacitance on the rgb lines to a minimum. the red, grn, blu terminals are identical, and any of the three terminals can be used to protect red, green, or blue video signals. en, en the device has dual complementary en and en enable inputs and can accept either active-low or active-high enable signals. pull en low and en high to place the device in shutdown (see the functional diagram/truth table ). v s output the device provides a current-limited voltage on v s when the part is enabled. v s is used as the pullup voltage for internal pullup resistors on sda1 and scl1, and can be used as an external supply. the internal pullup resistors from sda1 and scl1 to v s are active when the device is enabled, and are disabled when the device is in thermal shutdown (see the functional diagram/truth table ). the v s supply includes an internal resistor to discharge the supply when the device is in thermal shutdown or is disabled (see the functional diagram/truth table ). v s is current limited to prevent damage to host devices. when power is off (v cc = 0v), v s is protected against reverse- leakage current up to v s = +5.25v. thermal shutdown thermal-shutdown circuitry protects the device from overheating. the device enters thermal shutdown when the junction temperature exceeds +150 n c (typ) and returns to normal operation when the temperature drops by approximately +10 n c (typ) below the thermal-shut - down threshold. when the device is in thermal shutdown, both synch1 and syncv1 are pulled down to ground, the i 2 c level shifters are disabled, the sda1 and scl1 pullups are off, and the v s discharge resistor is on (see the functional diagram/truth table ). applications information power-supply decoupling bypass v cc and v s to ground with 1 f f ceramic capaci - tors as close as possible to the device. pcb layout high-speed switches such as the MAX14895E require proper pcb layout for optimum performance. ensure that impedance-controlled pcb traces for high-speed signals are matched in length and are as short as possible. connect the exposed pad to a solid ground plane. esd protection as with all maxim devices, esd protection structures are incorporated on all terminals to protect against elec - trostatic discharges encountered during handling and assembly. additionally, the device is protected to q 15kv on the red, grn, blu, en , v s , synch1, syncv1, scl1, and sda1 terminals by the hbm. for optimum esd performance, bypass v cc to ground with a 1 f f ceramic capacitor.
????????????????????????????????????????????????????????????????? maxim integrated products 9 MAX14895E enhanced vga port protector esd protection can be tested in various ways. the red, grn, blu, en , v s , synch1, syncv1, scl1, and sda1 terminals of the device are characterized for protection to the following limits: ? q 15kv using the hbm ? q 8kv using iec 61000-4-2 contact discharge human body model figure 2 shows the hbm. figure 3 shows the current waveform it generates when discharged into a low- impedance state. this model consists of a 100pf capaci - tor charged to the esd voltage of interest that is then discharged into the device through a 1.5k i resistor. iec 61000-4-2 the iec 6100-4-2 standard covers esd testing and per - formance of finished equipment. however, it does not specifically refer to integrated circuits. the device assists in designing equipment to meet iec 61000-4-2 without the need for additional esd protection components. the major difference between tests done using the hbm and iec 61000-4-2 is higher peak current in iec 61000- 4-2 because series resistance is lower in the iec 61000- 4-2 model. hence, the esd withstand voltage measured to iec 61000-4-2 is generally lower than that measured using the hbm. figure 4 shows the iec 61000-4-2 model, and figure 5 shows the current waveform for the iec 61000-4-2 esd contact discharge test. figure 2. human body esd test model figure 3. human body current waveform figure 4. iec 61000-4-2 esd test model figure 5. iec 61000-4-2 esd generator current waveform charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test 100% 36.8% t rl time t dl peak-to-peak ringing (not drawn to scale) i r 0 0 i peak (amps) 90% 10% charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test t r = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% i peak (amps)
???????????????????????????????????????????????????????????????? maxim integrated products 10 MAX14895E enhanced vga port protector ordering information + denotes lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package MAX14895Eete+t -40 n c to +85 n c 16 tqfn-ep* package type package code outline no. land pattern no. 16 tqfn-ep t1633+4 21-0136 90-0031
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 11 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX14895E enhanced vga port protector revision history revision number revision date description pages changed 0 3/11 initial release

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